Semiconductor integrated circuits communicate with each other over printed circuit board (PCB) traces using single-ended and differential signaling. Single ended signaling requires only one PCB trace and one pin on transmit and receive devices in case of point to point signaling and differential signaling requires two PCB traces and two pins on each of the transmit and receive devices. Although differential signaling requires twice as many pins and PCB traces as single ended signaling, it is often used in applications where noise immunity is important and for higher frequency signaling (typically over 150 MHz). With respect to voltage levels, input buffers can be designed for rail-to-rail (0 to Vdd) signaling such as Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) input buffers or sub rail-to-rail signaling as in Low Voltage Positive/Pseudo Emitter-coupled Logic (LVPECL), High-Speed Current Steering Logic (HCSL), Low Voltage Differential Signaling (LVDS) and Current Mode Logic (CML) inputs where input voltage swings around a predefined biasing voltage and the amplitude of the swing is lower than rail-to-rail voltage.
Although the majority of semiconductor devices require input buffers to be either single ended or differential, some devices require input buffers that can receive both single ended and differential signaling, such as Digital Phase Locked Loops (DPLLs), Field-Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). DPLLs typically need to terminate as many as possible input references with wide spread of input frequencies (from 1 Hz to 1 GHz). FPGAs and CPLDs on the other hand are generic devices, which need to handle various input formats and frequencies. Some of these devices have paired input pins so that two input pins can support either two single ended LVCMOS or one differential input.